1. Field of Invention
The present invention relates to a storage device including a nonvolatile memory and a computer system and a storage system provided with same, more particularly relates to an increase of speed of data transfer in a storage device including a flash memory.
2. Description of the Related Art
In recent years, flash memories are coming into attention as storage media of digital still cameras and portable computer devices.
A flash memory is a semiconductor memory using tunneling or hot electron acceleration to cause electrons to pass through a gate insulation film and inject them into a floating gate or trap layer to change a threshold value of a cell transistor and thereby to store data. A single transistor using a multilayer gate structure, an MNOS structure, etc. is sufficient for configuring a memory cell, therefore an inexpensive and large capacity memory can be realized. As a typical example of this, a NAND type flash memory can be explained.
FIG. 1 is a diagram showing an example of the internal configuration of a NAND type flash memory. In the NAND type flash memory of FIG. 1, a plurality of memory units 1-1 to 1-n connected to bit lines BL1 to BLn are arranged in an array state (vertically and horizontally). For example, a gate of a selection transistor 2 is connected to a selection gate line SL1, and a gate of a selection transistor 3 is connected to a selection gate line SL2. Further, gates of memory cells N0 to N15 are connected to word lines WL0 to WL15.
The memory cells N0 to N15 have multilayer gate structures and store data according to amounts of charges stored in the floating gates. Namely, when many electrons are stored in a floating gate, the threshold value of the transistor rises, therefore current penetration from any of the charged bit lines BL1 to BLn to the memory units 1 (-1 to -n) is detected at an access circuit 4 including a sense amplifier etc. to enable data judgment.
Such NAND type flash memory does not require provision of a contact region to the bit line for each memory cell, therefore is particularly suitable as a medium of a large capacity, inexpensive storage device.
In general, a flash memory has a very slow programming speed. Several hundred microseconds are taken per cell. Further, data cannot be overwritten, therefore it is necessary to erase data preceding programming. A long time up to a few milli (m) seconds is taken for this. This problem is handled by parallel processing of many memory cells.
Namely, for example, by simultaneously writing data in a block into a group of memory cells 5 connected to the same word line WL0 forming a page unit and erasing in a block all cell blocks 6 configured by a group of pages sharing memory units, the transfer speed of a program is improved.
Specifically, for example ISSCC 2002 Preprints, p. 106, session 6.4, discloses a 1 Gb NAND type flash memory. The page size here is 2 k bytes, and the erasure block size is 128 kB. Namely, by parallel erasing a group of memory cell of 128 k bytes in one memory array and programming the memory cells in parallel for each 2 k bytes, a program transfer speed of 10 MB/s is realized.
Further, in recent years, flash memories have been made multi-valued and have been further miniaturized. Along with this, the amounts of the signals have fallen. To deal with this, writing techniques with less of an adverse influence upon the non-selected cells have been studied and put into use.
For example in NAND type flash memories, ones limiting the write order of pages in an erasure block are becoming the mainstream. Japanese Patent Publication (A) No. 2002-260390 etc. disclose a write routine using the technique called “Local Self-Boost”. An example of such a write operation in the NAND type flash memory of FIG. 1 will be explained below.
For example, when writing data into the memory cell N1 and injecting electrons into the floating gate thereof, first, the front and rear word lines WL0 and WL2 sandwiching the memory cell N1 therebetween are set to 0V, the selection transistor 2 is turned on, and the selection transistor 3 is turned off. Here, the bit line BL1 is set to 0V, the adjacent bit line BL2 for which no write operation is desired is set to 3V, the selected word line WL1 is boosted up to 20V, and all word lines WL3 to WL15 other than that are boosted up to 10V. When using such a write routine, any node sandwiched between the word lines WL0 and WL2 of 0V and linked with a non-selected bit line is disconnected from the other nodes, receives a coupling from the word line WL1, and rises in potential up to about 10V.
On the other hand, for the selected memory cell N1, 0V applied to the bit line BL1 is transferred to a channel of the cell transistor N1 for writing just while the adjacent cell transistor N0 is in a depression state. Namely, when using the above write technique, the adjacent cell on the bit line side of a cell to be written in is erased and becomes a depression state. For this reason, it is an indispensable to erasing the entire block, then write data in the order of the memory cells N15, N14, N13, . . . , and N0.
In this way, recent large capacity flash memories tend not to allow random write operations even in page write operations and to require sequential writing from the higher address to the lower address in a block.